1. Field of the Invention
The present invention relates to semiconductor device fabrication processes and, in particular, to processes for the formation of dopant atom implanted regions.
2. Description of the Related Art
The fabrication of semiconductor devices often involves the processing of a semiconductor substrate (e.g. a silicon wafer) through a series of steps. Typically, this series of steps includes multiple ion implantation processes during which dopant atoms are introduced into and beyond the semiconductor substrate. The dopant atoms are added to the semiconductor substrate to form various semiconductor device regions, such as well regions, source and drain regions, and Lightly Doped Drain (LDD) extension regions. The dopant atoms are also added to modify the electrical characteristics of the semiconductor device, as in the case of Threshold Voltage (V.sub.T) adjust implants. See S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era, Volume 1--Process Technology, 280-283 (Lattice Press 1986), which is hereby incorporated by reference, for a further discussion of ion implantation processes.
V.sub.T adjust implant processes involve implanting dopant atoms into a channel region of an MOS transistor device to increase or decrease the net dopant atom concentration therein. It is well known in the semiconductor device fabrication field that V.sub.T adjust implants can be used to control the threshold voltage of the semiconductor device. See S. Wolf, Silicon Processing for the VLSI Era, Volume 2--Process Integration, 325 (Lattice Press 1990), and S. Wolf, Silicon Processing for the VLSI Era, Volume 3--The Submicron MOSFET, 183-187 (Lattice Press 1995), both of which are hereby incorporated by reference. As the length of a channel region (i.e. "channel length") of an MOS transistor device is reduced, however, the MOS transistor device becomes more susceptible to unwanted "punch-through" that results from a merging of source and drain depletion regions. Further, as the channel length is decreased, the MOS transistor device can experience two competing threshold voltage (V.sub.T) effects: one known as "V.sub.T roll-up" or "reverse short channel effect (RSCE)," and the other known as "V.sub.T roll-off." V.sub.T roll-up causes the V.sub.T of the MOS transistor device to increase with decreasing channel length, while V.sub.T roll-off causes the V.sub.T to decrease after reaching its maximum RSCE induced value. For a further discussion of punch-through and the RSCE, see S. Wolf, Silicon Processing for the VLSI Era, Volume 3--The Submicron MOSFET, 226 and 232-240 (Lattice Press 1995), which is hereby incorporated by reference. The result of these effects is that as the physical gate length (i.e. the width of the patterned polysilicon gate layer), and hence the channel length, of an MOS transistor device decreases, the electrical behavior of the MOS transistor device becomes more difficult to control. Conventional V.sub.T adjust implant processes can not address these V.sub.T roll-up and V.sub.T roll-off effects since they are conducted prior to the formation of the patterned polysilicon gate layer and are, therefore, independent of physical gate length.
There is, therefore, a need in the field for an implant process that forms physical gate length dependent dopant implanted regions and thereby provides for improved control of MOS transistor device performance (e.g. V.sub.T control).